| 发明名称 | Delay-insensitive asynchronous circuit | ||
| 摘要 | The asynchronous circuit includes a fork having at least two branches, each branch being connected to a logic gate so that the logic gate receives as input a branch-ending signal. It further includes a circuit for branching the branch-ending signal at the level of each logic gate to form a branched signal, and a blocking circuit comprising a Muller gate and receiving as input at least one branched signal, the blocking circuit being configured to prevent the propagation of an output signal when the branch-ending signals are in different logic states. | ||
| 申请公布号 | US8854075(B2) | 申请公布日期 | 2014.10.07 |
| 申请号 | US201313785770 | 申请日期 | 2013.03.05 |
| 申请人 | Tiempo | 发明人 | Renaudin Marc;Nguyen Van Mau David |
| 分类号 | H03K19/003;H03K19/177 | 主分类号 | H03K19/003 |
| 代理机构 | Oliff, PLC | 代理人 | Oliff, PLC |
| 主权项 | 1. An asynchronous circuit comprising: a fork having at least two branches, each branch being connected to a logic gate so that the logic gate receives as input a branch-ending signal; a circuit for branching the branch-ending signal at the level of each logic gate to form a branched signal; and a blocking circuit comprising a Muller gate and receiving as input at least one branched signal, the blocking circuit being configured to prevent the propagation of an output signal when the branch-ending signals are in different logic states. | ||
| 地址 | Montbonnot St-Martin FR | ||