| 发明名称 | Clock distribution systems for low power applications | ||
| 摘要 | Integrated circuit devices include first and second periodic signal generators and a power down detection circuit. The first periodic signal generator is configured to generate at least a first periodic signal having a first frequency at an output thereof and the second periodic signal generator is configured to generate a second periodic signal having a second frequency less than the first frequency at an output thereof. The power down detection circuit is configured to selectively provide one or the other of the first and second periodic signals to an output terminal of the integrated circuit device, in response to monitoring a status of a signal received at an input terminal of the integrated circuit device. This received signal reflects a power down status of an external device that receives the selected one of the first and second periodic signals. | ||
| 申请公布号 | US8854086(B1) | 申请公布日期 | 2014.10.07 |
| 申请号 | US201313795828 | 申请日期 | 2013.03.12 |
| 申请人 | Integrated Device Technology, Inc. | 发明人 | Bal Jagdeep;Hsiao Cheng Wen |
| 分类号 | G06F1/08;H03K3/012 | 主分类号 | G06F1/08 |
| 代理机构 | Myers, Bigel, et al. | 代理人 | Myers, Bigel, et al. |
| 主权项 | 1. An integrated circuit device, comprising: a first periodic signal generator configured to generate at least a first periodic signal having a first frequency at an output thereof; a second periodic signal generator configured to generate a second periodic signal having a second frequency less than the first frequency at an output thereof; and a power down detection circuit configured to selectively provide one or the other of the first and second periodic signals to an output terminal of the integrated circuit device, in response to monitoring a status of a signal received at an input terminal of the integrated circuit device that reflects a power down status of an external device configured to receive the selected one of the first and second periodic signals. | ||
| 地址 | San Jose CA US | ||