Persistent prefetch data stream settings

摘要

A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.

主权项

1. A system comprising:
a processor core; cache coupled with the core; a transience register adapted to host an indication of transient for data stream prefetching; a prefetch unit adapted to monitor the transience register and adapted to generate prefetch requests of data streams with an indication of transient when the transience register indicates transient for data stream prefetching and adapted to generate prefetch requests without the indication of transient when the transience register does not indicate transient; a cache controller coupled with the prefetch unit, the cache controller adapted to implement a cache replacement policy and cache coherence protocol, adapted to write data supplied from memory responsive to the prefetch requests into the cache with an indication of transient, and adapted to victimize cache lines of the cache with an indication of transient independent of the cache replacement policy.