Write self timing circuitry for self-timed memory

摘要

A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.

主权项

1. A circuit, comprising:
a memory cell array including:
a first section having a plurality of memory cells and at least one data bit line for each column of memory cells in said first section; anda second section having a plurality of write timer cells arranged in a column, each write timer cell including an internal true node, an internal complement node and a pullup transistor having a gate terminal coupled to said internal true node, said second section including at least one reference bit line coupled to the column of write timer cells and having a true reference internal line coupled to the internal true nodes of the column of write timer cells;column circuitry coupled to the first and second sections of the memory cell array, said column circuitry including a reference write driver circuit having an output coupled to drive said at least one reference bit line; andmeans for lowering a gate to source voltage of the write timer cell pullup transistor by raising a lower voltage level to which said internal true node is pulled down during a write operation to a voltage level above logic low level.