| 发明名称 | Multi-phase clock generation circuit | ||
| 摘要 | A multi-phase clock generation circuit includes a first clock buffer unit configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock, and a second clock buffer unit configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock. | ||
| 申请公布号 | US8854093(B2) | 申请公布日期 | 2014.10.07 |
| 申请号 | US201313845181 | 申请日期 | 2013.03.18 |
| 申请人 | SK Hynix Inc. | 发明人 | Lee Sang Kwon |
| 分类号 | H03L7/00;H03K5/15 | 主分类号 | H03L7/00 |
| 代理机构 | William Park & Associates Patent Ltd. | 代理人 | William Park & Associates Patent Ltd. |
| 主权项 | 1. A multi-phase clock generation circuit comprising: a first clock buffer unit configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock; and a second clock buffer unit configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock, wherein the first clock buffer unit comprises a first buffer section configured to invert and buffer the first internal clock in synchronization with a first edge of the external clock, and to output the fourth internal clock to a first node, and a second buffer section configured to invert and buffer the second internal clock in synchronization with the first edge of the external clock, and to output the third internal clock to a second node. | ||
| 地址 | Gyeonggi-do KR | ||