发明名称 Computational process control
摘要 The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.
申请公布号 US8856694(B2) 申请公布日期 2014.10.07
申请号 US201213481564 申请日期 2012.05.25
申请人 ASML Netherlands B.V. 发明人 Ye Jun;Cao Yu;Koonmen James Patrick
分类号 G06F17/50;G05B13/04;G03F7/20 主分类号 G06F17/50
代理机构 Pillsbury Winthrop Shaw Pittman LLP 代理人 Pillsbury Winthrop Shaw Pittman LLP
主权项 1. A computer-implemented method of controlling a lithography process by reducing a temporal drift of a performance of a lithography apparatus used for the lithography process, the method comprising: (a) defining baseline performance of the lithography apparatus, where a lithography model for the baseline performance is obtained using a first set of wafer metrology data collected from exposed patterns using the lithography process at an initial time, and wherein the lithography model is configured to simulate variations of one or more lithography process parameters in relation to one or more settings of the lithography apparatus; (b) monitoring a performance stability of the lithography apparatus by analyzing the temporal drift associated with a current performance of the lithography apparatus with respect to the baseline performance, wherein the temporal drift is determined by comparing the wafer metrology data collected at the initial time, and subsequent wafer metrology data collected from exposed patterns at a subsequent time; and (c) adjusting the one or more settings of the lithography apparatus to reduce the determined temporal drift by reducing the difference between the baseline performance and the current performance, thereby maintaining the lithography process within or substantially close to the defined baseline performance, wherein one or more steps of the method are performed by using a computer.
地址 Veldhoven NL