Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures

摘要

A processing apparatus comprises logic to, according to a selected secure hash algorithm (SHA) algorithm, generate hash values by preparing message schedules for a plurality of message blocks in parallel using single instruction multiple date (SIMD) instructions and performing compression in serial, and logic to generate a message digest conforming to the secure hash algorithm (SHA) algorithm.

主权项

1. A processor comprising:
a controller to, according to a selected secure hash algorithm (SHA) algorithm, generate hash values by preparing message schedules for a plurality of message blocks in parallel using single instruction multiple date (SIMD) instructions and performing compression in serial; and circuits to generate a message digest conforming to the secure hash algorithm (SHA) algorithm, wherein each of the message schedules is designated for use in the compression for one of the plurality of message blocks, each of the message schedules is derived based upon more than one of the plurality of the message blocks, and more than one of the plurality of the message blocks are processed using single instruction multiple data (SIMD) instructions in each of a plurality of loop iterations to derive respective ones of the message schedules.