Transmitters and receivers using a jitter-attenuated clock derived from a gapped clock reference

摘要

A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

主权项

1. A method for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock, comprising:
using a first reference clock having a first frequency, generating an asynchronous gapped clock having an average second frequency less than the first frequency; a first-in first-out (FIFO) memory accepting the gapped clock and loading an input serial stream of data at a rate responsive to the gapped clock; iteratively calculating a dynamic numerator (DN) and dynamic denominator (DD) for the gapped clock; averaging DN and DD; in response to the averaging, generating an averaged numerator (AN) and an averaged denominator (AD); multiplying the first frequency by a ratio AN/AD to create a jitter-attenuated second clock having the second frequency; the FIFO memory accepting the jitter-attenuated second clock and supplying data from memory at the second frequency; a framer accepting the data from the FIFO memory and the jitter-attenuated second clock; synchronizing the data with the jitter-attenuated second clock, and transmitting a serial stream of output data; and generating a divided clock with a uniform minimum divide period of (MD); wherein accepting the first reference clock comprises accepting a frame of (n) clock cycles; generating the asynchronous gapped clock comprises dividing (n) by an integer number (x) of instantaneous gap clock periods (IGCPs), where the total number of clock gaps in the (x) IGCPs is (m); and iteratively calculating DN comprises calculating:
(x)(MD)+(m)=(n), when (x)(MD)≧n; and,(x)(MD)−(m)=(n), when (x)(MD)