发明名称 CLOCK PHASE INTERPOLATION CIRCUIT AND DATA TRANSMISSION/RECEPTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a phase interpolation circuit that continuously keeps an optimum operating band irrespective of PVT variations.SOLUTION: The clock phase interpolation circuit for generating phase-interpolated interpolation clocks PI_CLK, PI_CLKX from a plurality of operation clocks CLK_0, CLK_90, CLK_180, CLK_270 different in phase includes: a phase interpolation processing circuit having band adjustment elements 15A, 15B, 16A, 16B therein and capable of changing set values of the band adjustment elements to perform a band adjustment; and a control circuit 20 for detecting a transition state of the interpolation clocks relative to a reference clock PLL_CLK, and on the basis of the detected transition state, controlling the set values of the band adjustment elements.
申请公布号 JP2014192588(A) 申请公布日期 2014.10.06
申请号 JP20130064459 申请日期 2013.03.26
申请人 FUJITSU LTD 发明人 YAMAGUCHI HISAKATSU
分类号 H03L7/06;H03L7/00;H04L7/02 主分类号 H03L7/06
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