发明名称
摘要 Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results.
申请公布号 JP2014526757(A) 申请公布日期 2014.10.06
申请号 JP20140531780 申请日期 2011.09.26
申请人 发明人
分类号 G06F17/16;G06F9/30;G06F9/38 主分类号 G06F17/16
代理机构 代理人
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