| 摘要 |
A coherence management circuit includes: an arbitration unit which receives request signals from a plurality of cores and provides one among the request signal; a coherence management unit which provides the arbitration unit with requested data corresponding to the provided request signal among cache lines of cache memories, and which maintains the coherence of the data stored in the cache memories; and a directory memory which includes a plurality of directory lines each of which at least comprises a pivot field, where an identifier of a reference cache memory accessing at least one memory entry among the cache memories is written, and a pattern field, where present bits indicating whether to share the at least one memory entry of the cache memories within a predetermined range (pattern window) from the reference cache memory, based on the reference cache memory are written. The coherence management unit controls the directory memory, and maintains the coherence of the data with reference to the directory memory. |
