发明名称 DESCRAMBLE CIRCUIT AND DESCRAMBLE METHOD
摘要 PROBLEM TO BE SOLVED: To provide a descramble circuit and a descramble method, establishing scrambler synchronization with a small amount of synchronous data.SOLUTION: The descramble method includes: detecting synchronous data from a signal scrambled by a transmission-side scrambler; starting to output a first scramble code from a plurality of first scramblers, having each shift direction of a shift register opposite to the direction of the transmission-side scrambler, whenever the synchronous data is detected; detecting the synchronous timing of a part of each first scramble code output from the plurality of first scramblers simultaneously coincident with the synchronous data detected according to the output start timing; and starting to output a second scramble code for descrambling the signal, according to the synchronous timing.
申请公布号 JP2014192886(A) 申请公布日期 2014.10.06
申请号 JP20130069787 申请日期 2013.03.28
申请人 FUJITSU LTD 发明人 TSUZUKI TOSHIHIDE
分类号 H04L7/00;H04L7/08 主分类号 H04L7/00
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