METHOD OF PACKAGING A CHIP AND A SUBSTRATE

摘要

Disclosed is a method of packaging a chip and a substrate, including the steps of forming a substrate with a thickness ranging from 70 to 150 μm, which comprises a dielectric layer, a circuit metal layer stacked on the dielectric layer and bonding pads higher than the dielectric layer by 10 to 15 μm; forming a stabilizing structure around the substrate to provide a receiving space; disposing the chip on the receiving space and bonding the pins of the chip with the bonding pads; and filling up the receiving space under the chip with a filling material to a total thickness ranging from 300 to 850 μm. Without the plastic molding process, the present invention reduces the cost and the total thickness, and further prevents the substrate from warping by use of the stabilizing fixing structure.

主权项

1. A method of packaging a chip and a substrate, comprising steps of:
forming a thin chip substrate with a thickness ranging from 70 to 150 μm, said thin chip substrate including a dielectric layer, a first circuit metal layer, a second circuit metal layer and bonding pads, wherein the first circuit metal layer is inlaid into the dielectric layer such that the first circuit metal layer and the dielectric layer forms a co-plane, the second circuit metal layer is connected to the first circuit metal layer through holes formed in the dielectric layer while the bonding pads are higher than the co-plane by 10 to 15 μm and are connected to the first circuit metal layer; forming a stabilizing structure around the thin chip substrate on the co-plane to provide a receiving space for disposing the chip, wherein the stabilizing structure includes a stabilizing layer formed on an adhesive layer with the adhesive layer disposed between the stabilizing layer and the co-plane; disposing the chip in the receiving space of the thin chip substrate and soldering pins of the chip with the bonding pads; and injecting a filling material to fill up the receiving space under the chip to stabilize the pins of the chip and the bonding pads such that a packaged structure with a total thickness ranging from 300 to 850 μm is formed; wherein the stabilizing layer is formed with a top higher than the top of the chip so as to prevent the chip from warping and distortion.