RECEPTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To suppress generation of tracking errors.SOLUTION: A burst mode CDR 11 detects an edge from a data signal on which a clock is superposed, and a voltage-controlled oscillator 22 whose oscillation operation is reset on the basis of a timing when the edge is detected generates a reproduction clock. A phase adjustment part 12 adjusts a phase of the data signal so as to be accorded with a phase of the reproduction clock. A PLL type CDR 13 adjusts an oscillation frequency of the reproduction clock by the voltage-controlled oscillator 22 on the basis of a phase difference between a data signal whose phase is adjusted by the phase adjustment part 12, and a feedback clock from the voltage-controlled oscillator 22. A determination part 15 determines a value of the data signal at a timing when a signal level of the reproduction clock makes a transition.