| 发明名称 |
APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY |
| 摘要 |
An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core. |
| 申请公布号 |
US2014298140(A1) |
申请公布日期 |
2014.10.02 |
| 申请号 |
US201113994105 |
申请日期 |
2011.12.22 |
| 申请人 |
Yigzaw Theodros;Lempel Oded;Hafi Hisham;Santhanakrisnan Geeyarpuram N;Vargas Jose A;Srinivasa Ganapati N;Kumar Mohan J;Novakovsky Larisa;Rappoport Lihu;Koren Chen;Mandelblat Julius Yuli |
发明人 |
Yigzaw Theodros;Lempel Oded;Hafi Hisham;Santhanakrisnan Geeyarpuram N;Vargas Jose A;Srinivasa Ganapati N;Kumar Mohan J;Novakovsky Larisa;Rappoport Lihu;Koren Chen;Mandelblat Julius Yuli |
| 分类号 |
G06F11/10 |
主分类号 |
G06F11/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for detecting and recovering from instruction fetch errors within a processor core comprising:
detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core. |
| 地址 |
Sherwood OR US |
