发明名称 |
Circuit and Method for Testing Memory Devices |
摘要 |
The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines. The circuit comprises: a test pattern generator coupled to a first portion of the plurality of address lines to receive test data, and configured to store the test data and to generate a write test vector and a read test vector according to the test data, wherein the write test vector is associated with the read test vector; a multiplexer coupled to the test pattern generator, and configured to selectively transmit the write test vector to a subject block of the multiple memory blocks to enable the write test vector to be written into the subject block; and a comparator coupled to the test pattern generator and the subject block, and configured to compare the read test vector with a readout signal generated from the subject block and the write test vector, and to generate a flag indicative of the comparison result. |
申请公布号 |
US2014298120(A1) |
申请公布日期 |
2014.10.02 |
申请号 |
US201414225438 |
申请日期 |
2014.03.26 |
申请人 |
Integrated Silicon Solution (Shanghai), Inc |
发明人 |
Tong Mingzhao |
分类号 |
G11C29/10 |
主分类号 |
G11C29/10 |
代理机构 |
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代理人 |
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主权项 |
1. A circuit for testing a memory device having multiple memory blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines, comprising:
a test pattern generator coupled to a first portion of the plurality of address lines to receive test data, and configured to store the test data and to generate a write test vector and a read test vector according to the test data, wherein the write test vector is associated with the read test vector; a multiplexer coupled to the test pattern generator, and configured to selectively transmit the write test vector to a subject block of the multiple memory blocks to enable the write test vector to be written into the subject block; and a comparator coupled to the test pattern generator and the subject block, and configured to compare the test vector with a readout signal generated from the subject block and the write test vector, and to generate a flag indicative of the comparison result. |
地址 |
Shanghai CN |