MEMORY CONTROLLER AND ASSOCIATED METHOD FOR GENERATING MEMORY ADDRESS

摘要

A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.

主权项

1. A memory controller, connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit, comprising:
a mapping unit, configured to convert a system address generated by the accessing unit into a memory address and to transmit the memory address to the DDR DRAM; wherein, a burst length of the DDR DRAM is L and L=2x, an (x+1)th bit from a least significant bit (LSB) of the memory address is in a bank group address, and L and x are positive integers.