SYNCLESS UNIT INTERVAL VARIATION TOLERANT PWM RECEIVER CIRCUIT, SYSTEM AND METHOD

摘要

A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal.

主权项

1. A method of demodulating a PWM signal, comprising:
receiving the pulse width modulated signal, the pulse width modulated signal having a unit interval and a duty cycle defined over this unit interval by a low portion and high portion; using the received pulse width modulated signal as a clock signal to control the integration of a current during the respective low and high portions of the duty cycle of the pulse width modulated signal; and demodulating the pulse width modulated signal using the integrated currents during the low and high portions of the duty cycle of the pulse width modulated signal.