DIGIT LINE EQUILIBRATION USING ACCESS DEVICES AT THE EDGE OF SUB-ARRAYS

摘要

A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other.

主权项

1. An apparatus, comprising:
a memory sub-array including memory cells located along digit lines; a first sense amplifier block and a second sense amplifier block operably coupled with the memory sub-array on opposing sides of the memory sub-array, wherein the digit lines include:
a first digit line including:
a terminated end coupled with the first sense amplifier block; andan unterminated end proximate the second sense amplifier block;a second digit line including:
a terminated end coupled with the second sense amplifier block; andan unterminated end proximate the first sense amplifier block; and an equilibrate boosting circuit configured to couple the terminated end of the first digit line and the unterminated end of the second digit line responsive to an equilibrate boosting signal.