| 摘要 |
A high-voltage heavy-current drive circuit applied in a power factor corrector, comprising a current mirroring circuit (1), a level shift circuit (3), a high-voltage pre-modulation circuit (2), a dead time control circuit (4) and a heavy-current output stage (5); the heavy-current output stage adopts a Darlington output stage structure to increase the maximum operating frequency of the drive circuit. The stabilized breakdown voltage characteristic of a voltage stabilizing diode is utilized to ensure the drive circuit operating within a safe voltage range. Adding dead time control into the level shift circuit not only prevents the momentary heavy-current from a power supply to the ground during the level conversion process, but also reduces the static power consumption of the drive circuit. |
| 主权项 |
1. A high-voltage heavy-current drive circuit applied in a power factor corrector, comprising a current mirror circuit (1), a high-voltage pre-modulation circuit (2), a level shift circuit (3), a dead time control circuit (4), and a heavy-current output stage (5);
wherein the current mirror circuit (1) is configured to convert an input signal Ibias to an input signal of the high voltage pre-modulation circuit using a current source circuit and a current sink circuit composed of a plurality of resistors and transistors, the input signal Ibias is generated by a starting current Istart and a reference current source, and the starting current Istart is converted to an input signal of the level shift circuit; under an effect of a bias of the current mirror circuit (1), the high voltage pre-modulation circuit (2) is configured to convert a high input supply voltage VDD to a relative low voltage using an isolation of a high-voltage LDMOS transistor and stabilized breakdown voltage characteristics of a zener diode to ensure the drive circuit operating within a safe voltage range, and to generate an input voltage VCLAMP of the level shift circuit; under effects of an output of the high-voltage pre-modulation circuit (2) and the bias of the current mirror circuit (1), the level shift circuit (3) is configured to control on and off states of a high-voltage transistor PMOS and a high-voltage transistor NOMS using a first logic switch signal S1 and a second switch logic Signal S2 generated by the dead time control circuit; thereby generating an output signal Vs of the level shift circuit to provide a logic switch signal for the heavy-current output stage; under an effect of an digital logic drive signal, using delays of a logic gate circuit and capacitors, the dead time control circuit (4) is configured to generate inverse non-overlapping first logic switch signal S1 and second logic switch signal S2, and to control operating states of the level shift circuit and the heavy-current output stage; under an effect of a Darlington composed of high voltage transistors, using the logic switch signal VS generated by the high-voltage transistor NOMS and the level shift circuit and a second logic switch signal S2 generated by the dead time control circuit, the high current output stage (3) is configured to generate an output drive signal GATE_DRIVER with great source current capability and sink current capability and to drive on and off states of an external power device. |
