INTEGRATED CIRCUIT WITH REDUCED POWER CONSUMPTION IN A TEST MODE, AND RELATED METHODS

摘要

An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.

主权项

1. An integrated circuit comprising:
N number of functional logic blocks, with N being greater than or equal to two, and with said N number of functional logic blocks configured to receive scan-ins and generate scan-outs during testing; and clock staggering test circuitry, when in a shift mode, configured to generate N staggered shift clock signals for respective ones of said N functional logic blocks, each of the N staggered shift clock signals having a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N.