SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS
摘要
Technologies for system management interrupt ("SMI") handling include a number of processor cores configured to enter a system management mode ("SMM") in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.
申请公布号
WO2014158603(A1)
申请公布日期
2014.10.02
申请号
WO2014US18664
申请日期
2014.02.26
申请人
INTEL CORPORATION;JAYAKUMAR, SARATHY;KUMAR, MOHAN J.;KINNEY, MICHAEL D.
发明人
JAYAKUMAR, SARATHY;KUMAR, MOHAN J.;KINNEY, MICHAEL D.