发明名称 FAULT-TOLERANT SYSTEM AND FAULT-TOLERANT OPERATING METHOD
摘要 A fault-tolerant system including a calculation unit and an output synthesizer is provided. The calculation unit receives a first environmental parameter and input data, wherein the calculation unit further includes a first and a second calculation circuits. The first calculation circuit is arranged to perform a calculation on the input data in response to the first environmental parameter to generate a first calculation result. The second calculation circuit is different from the first calculation circuit, and arranged to perform the calculation on the input data in response to the first environmental parameter to generate a second calculation result. The output synthesizer selects a first and a second set of bits from the first and the second calculation result according to a control signal, and synthesizes the first set of bits and the second set of bits in sequence to generate an adjusted calculation result.
申请公布号 US2014297995(A1) 申请公布日期 2014.10.02
申请号 US201314054643 申请日期 2013.10.15
申请人 Industrial Technology Research Institute 发明人 Chang Yung-Chang;Liu Hsing-Chuang;Yang Chih-Jen
分类号 G06F9/30 主分类号 G06F9/30
代理机构 代理人
主权项 1. A fault-tolerant system, comprising: a calculation unit, arranged to receive input data and a first instruction, wherein the calculation unit further comprises: a first calculation module, comprising a first calculation circuit arranged to perform a calculation on the input data in response to a first environmental parameter to generate a first calculation result, wherein the first calculation result is constituted by a plurality of first output bits, and each of the first output bits has a corresponding bit position; anda second calculation module, comprising a second calculation circuit different from the first calculation circuit, and the second calculation circuit is arranged to perform the calculation on the input data in response to the first environmental parameter to generate a second calculation result, wherein the second calculation result is constituted by a plurality of second output bits, and each of the second output bits has a corresponding bit position; and an output synthesizer, arranged to select a first set of bits from the first output bits and a second set of bits from the second output bits according to a control signal, and synthesize the first set of bits and the second set of bits in sequence according to the corresponding bit positions of the first set of bits in the first output bits and the second set of bits in the second output bits to generate an adjusted calculation result.
地址 Hsinchu TW