Memory Controllers, Systems, and Methods Supporting Multiple Request Modes

摘要

A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

主权项

1. A memory controller to direct requests to sections of a memory die, via respective channels, the memory controller comprising:
for each one of the respective channels, at least one queue to schedule issuance of respective ones of the requests to a corresponding one of the sections of the memory die; logic to receive the requests from a host and to steer each request to the at least one queue for one of the respective channels according to a corresponding one of the sections of the memory die to be accessed according to the request; and for each one of the respective channels, interface circuitry to transmit requests from the at least one queue to the corresponding one of the sections, via the one of the respective channels.