SiGe SRAM BUTTED CONTACT RESISTANCE IMPROVEMENT

摘要

The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.

主权项

1. A method, comprising:
forming a first gate structure over a first active region of a substrate to form a first transistor, wherein the first gate structure also extends at least partially over a second active region of the substrate to establish a dummy gate over the second active region; forming a second gate structure over the second active region to form a second transistor; forming a recess within the second active region between the dummy gate and the second gate structure; forming a source/drain region within the recess; and forming a butted contact to couple the source/drain region to the dummy gate.