Erase Techniques and Circuits Therefor for Non-Volatile Memory Devices

摘要

Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.

主权项

1. A device comprising:
a memory array including a plurality of memory cells; an erase pulse circuit configured to supply the memory array with a first erase pulse in response to a first control information and with a second erase pulse in response to a second control information, the second erase pulse being higher in voltage level than the first erase pulse; and a control circuit configured to produce the first control information in order to bring each of the memory cells of the memory array into an erased state, the control circuit being further configured to produce the first control information at least one more time when at least one of the memory cells has not been brought into the erased state, the control circuit being further configured to produce the second control information when at least one of the memory cells has not still been brought into the erased state irrespective of having been supplied with the first erase pulse twice or more times.