发明名称 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
摘要 A system and method are described for intelligently flushing data from a processor cache. For example, a system according to one embodiment of the invention comprises: a processor having a cache from which data is flushed, the data associated with a particular system address range; and a PCM memory controller for managing access to data stored in a PCM memory device corresponding to the particular system address range; the processor determining whether memory flush hints are enabled for the specified system address range, wherein if memory flush hints are enabled for the specified system address range then the processor sending a memory flush hint to a PCM memory controller of the PCM memory device and wherein the PCM memory controller uses the memory flush hint to determine whether to save the flushed data to the PCM memory device.
申请公布号 US2014297919(A1) 申请公布日期 2014.10.02
申请号 US201113994723 申请日期 2011.12.21
申请人 Nachimuthu Murugasamy K;Kumar Mohan J 发明人 Nachimuthu Murugasamy K;Kumar Mohan J
分类号 G11C14/00 主分类号 G11C14/00
代理机构 代理人
主权项 1. A method for utilizing memory flush hints within a computer system comprising: flushing data from a processor cache; determining whether memory flush hints are enabled for a specified system address range allocated to a phase change memory (“PCM”) memory device; if the memory flush hints are enabled for the specified system address range then generating a memory flush hint for a PCM memory controller of the PCM memory device; and using the memory flush hint to determine whether to save the flushed data to the PCM memory device.
地址 Beaverton OR US