MULTI-THRESHOLD DUAL-SPACER DUAL-RAIL DELAY-INSENSITIVE LOGIC (MTD3L) CIRCUIT DESIGN

摘要

A Multi-Threshold Dual-spacer Dual-rail Delay-insensitive Logic (MTD3L) circuit architecture. The architecture includes a first th22 circuit, a second th22 circuit, and an XNOR gate. The first th22 circuit is configured to receive a first rail input, a completion detection signal, and a reset signal, and to produce a first rail output. The second th22 circuit is configured to receive a second rail input, the completion detection signal, and the reset signal, and to produce a first rail output. The XNOR gate is configured to receive the first rail input and the second rail input and to produce a completion detection signal output.

主权项

1. A Multi-Threshold Dual-spacer Dual-rail Delay-insensitive Logic (MTD3L) circuit comprising:
a first circuit coupled to VDD; a second circuit coupled to ground and the first circuit, the coupling to the first circuit forming a common coupling; a first pmos transistor having a source coupled to VDD and a gate coupled to a sleep-to-0 input; a first nmos transistor having a drain coupled to ground and a gate coupled to a complement of a sleep-to-1 input; a second pmos transistor having a source coupled to a drain of the first pmos transistor and a gate coupled to the common coupling; a second nmos transistor having a drain coupled to a source of the first nmos transistor and a gate coupled to the common coupling; a third pmos transistor having a source coupled to the drain of the first pmos transistor and a gate coupled to the complement of the sleep-to-1 input; a third nmos transistor having a drain coupled to the source of the first nmos transistor and a gate coupled to the sleep-to-0 input; and an output coupled to a drain of the second pmos transistor, a drain of the third pmos transistor, a source of the second nmos transistor, and a source of the third nmos transistor.