DOUBLE QC-LDPC CODE

摘要

A double quasi-cyclic low density parity check (DQC-LDPC) code and a corresponding processor are disclosed herein. The parity-check matrix of DQC-LDPC codes has regularity with its corresponding processor including an input end, an output end and a processing module. The parity-check matrix includes a double quasi-cyclic matrix. The double quasi-cyclic matrix includes a plurality of sub-matrices. The sub-matrices are arranged in an array. Each sub-matrix includes a plurality of entries, and each sub-matrix is a circulant matrix having the entries circular shifted row-by-row. The double quasi-cyclic matrix is a circulant matrix having the sub-matrices circular shifted row-by-row. The processing module is configured to process an input signal and output an output signal correspond to the parity-check matrix of a low density parity check code (LDPC).

主权项

1. A processor corresponding to a double quasi-cyclic low density parity check (DQC-LDPC) code, wherein the processor comprises:
an input end configured to receive an input signal; an output end configured to output an output signal; and a processing module configured to process the input signal to generate the output signal corresponding to a parity-check matrix of the DQC-LDPC code, wherein the parity-check matrix comprises a double quasi-cyclic (DQC) matrix, the double quasi-cyclic matrix comprises a plurality of sub-matrices, the sub-matrices are arranged in an array, each sub-matrix comprises a plurality of entries, each sub-matrix is a circulant matrix having the entries circular shifted row-by-row, and the double quasi-cyclic matrix is a circulant matrix having the sub-matrices circular shifted row-by-row.