Cost-Effective Gate Replacement Process

摘要

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

主权项

1. A semiconductor device, comprising:
a substrate; an NMOS gate disposed over the substrate, wherein the NMOS gate includes: a first high-k gate dielectric, a capping layer disposed over the first high-k gate dielectric, and an N-type work function metal disposed over the capping layer, and a polysilicon gate electrode disposed over the N-type work function metal, wherein the capping layer and the N-type work function metal are configured to collectively tune a work function of the NMOS gate; and a PMOS gate disposed over the substrate and adjacent to the NMOS gate, wherein the PMOS gate includes: a second high-k gate dielectric, and a P-type metal gate electrode disposed over the second high-k gate dielectric, wherein a portion of the P-type metal gate electrode is configured to tune a work function of the PMOS gate.