| 摘要 |
Provided is a method of manufacturing a semiconductor device structure comprising: a step of providing a substrate which includes an active area and an isolation area, a first gate electrode structure on the upper side of the active area, a second gate electrode structure as a dummy gate electrode structure on the upper side of the isolation area, a spacer structure at both sides of the first gate electrode structure and both sides of the second gate electrode structure, and a gate electrode mask layer at least on the upper surface of the second gate electrode structure; a step of forming an inner interconnection material layer on the upper sides of the first and the second gate electrode structures, and the substrate; an etching step of forming an inner interconnection layer which is electrically isolated from the first and the second gate electrode structures by etching and removing all the inner interconnection material layers disposed on the first gate electrode structure; and a step of forming a source/drain area contact hole on the inner interconnection layer. The present invention improves the utilization rate of a semiconductor chip and reduces semiconductor manufacturing costs by reducing the size of a semiconductor device since a gap between a gate electrode structure and an STI structure can be reduced. [Reference numerals] (S101) Provide a substrate on which a first and second gate electrode structures, a spacer structure, and a gate electrode mask layer placed on the first and second gate electrode structures are formed; (S102) Form an inner interconnection material layer; (S103) Form an inner interconnection layer electrically isolated from the first and second gate electrode structures; (S104) Form a source/drain area contact hole on the inner interconnection layer |
