SPDIF clock and data recovery with sample rate converter

摘要

A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

主权项

1. A data recovery system, comprising:
a first clock signal generator to generate a first clock signal comprising a frequency that is greater than or equal to an expected frequency of an input data stream; a sample counter to increment a sample count in response to a sample received in the input data stream and to decrement the sample count in response to a second clock signal; and a second clock signal generator to generate the second clock signal from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.