Synchronous multiple port memory with asynchronous ports

摘要

A method of operating a multiport memory, which has first and second sets of word lines and bit lines for accessing a memory array, uses a first port and a second port for accesses during a first phase of a master clock and a third port and a fourth port during a second phase of the master clock. Each port has its own port clock, which clocks their own row and column addresses, that is no faster than the master clock. Assuming there is demand for it, four accesses occur for each cycle of the master clock. This has the effect of being able to be sure that a given access is complete within two cycles of the port clocks and can be operated at the rate of one access per cycle of the port clock.

主权项

1. A method, comprising:
providing a memory system comprising a first port a second port, a third port, a fourth port, an array of memory cells, a first set of word lines and bit lines coupled to the memory cells, a second set of word lines and bit lines coupled to the memory cells, and a system clock in which each cycle has a first phase and a second phase; applying a first clock, a first row address, and a first column address to the first port; applying a second clock, a second row address, and a second column address to the second port; applying a third clock, a third row address, and third column address, to the third port; applying a fourth clock, a fourth row address, and a fourth column address to the fourth port; and performing accesses to the array through:
the first port responsive to the system clock entering the first phase of a first cycle of the system clock and the first clock being active using the first set of word lines and bit lines during the first phase of the first cycle;the second port responsive to the system clock entering the first phase of the first cycle and the second clock being active using the second set of word lines and bit lines if the first row address is different from the second row address during the first phase of the first cycle;the third port responsive to the system clock entering the first phase of the first cycle and the third clock being active using the first set of word lines and bit lines during the second phase of the first cycle; andthe fourth port responsive to the system clock entering the first phase of the first cycle and the fourth clock being active using the second set of word lines and bit lines if the third row address is different from the fourth row address during the second phase of the second cycle.