Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof

摘要

Embodiments described herein generally relate to verifying that a FLASH memory has been erased. In an embodiment, a method of erase verifying a memory column of a FLASH memory includes applying a pass gate voltage to even numbered memory transistors while applying an erase verify voltage to the odd numbered memory transistors. Applying a string current to the memory column allows a probe to determine if the string current is successfully traversing the memory column, and thus verifying that the odd numbered memory transistors were erased. The even numbered memory transistors are verified in the following cycle.

主权项

1. A method for erase verify of at least a portion of a memory column, the memory column including an arrangement of memory transistors, the method comprising:
applying an erase voltage to the memory column; applying an erase verify voltage to first memory transistors in the memory column while applying a pass gate voltage to second memory transistors in the memory column; reading a verification electrical level to determine whether any of the first memory transistors were not successfully erased; applying the erase verify voltage to third memory transistors in the memory column while applying the pass gate voltage to fourth memory transistors in the memory column; and reading the verification electrical level to determine whether any of the third memory transistors were not successfully erased.