Method of decomposable checking approach for mask alignment in multiple patterning

摘要

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a first plurality of features defined in a first layer and a second plurality of features defined in a second layer; converting the IC design layout to a topological diagram having nodes, chains and arrows; and identifying alignment conflict based on the topological diagram using rules associated with loop and path count.

主权项

1. A method comprising:
receiving an integrated circuit (IC) design layout having a first plurality of features defined in a first layer and a second plurality of features defined in a second layer, wherein the first layer corresponds to a first material layer, and wherein the second layer corresponds to a second material layer; converting, by a computer system, the IC design layout to a topological diagram having nodes, chains and arrows; and identifying alignment conflict based on the topological diagram using rules associated with loop and path count, wherein in the topological diagram an arrow represents a mask alignment relation between two features in the first and second layers, respectively, and links the two features.