Power device integration on a common substrate

摘要

A MOSFET includes an active region formed on an SOI substrate. A buried well is formed in the active region. A drain region having the first conductivity type is formed in the active region and spaced laterally from a source region and the buried well. A body region is formed in the active region between the source and drain regions on the buried well, and a drift region is formed in the active region between the drain and body regions on at least a portion of the buried well. A shielding structure is formed proximate the upper surface of the active region, overlapping a gate. During conduction, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes the drift region. The MOSFET is configured to sustain a linear mode of operation of an inversion channel formed under the gate.

主权项

1. A semiconductor structure comprising at least one radio frequency (RF) metal-oxide-semiconductor (MOS) transistor, the at least one RF MOS transistor comprising:
a first insulating layer formed on a substrate; an active region having a first conductivity type formed on at least a portion of the first insulating layer; a buried well having a second conductivity type formed in the active region; a source region having the first conductivity type formed in the active region proximate an upper surface of the active region, the source region being electrically connected with the buried well; a drain region having the first conductivity type formed in the active region proximate the upper surface of the active region and spaced laterally from the source region and the buried well; a body region having the second conductivity type formed in the active region between the source and drain regions on at least a portion of the buried well, at least a portion of the source region extending laterally into the body region; a drift region having the first conductivity type formed in the active region between the drain and body regions on at least a portion of the buried well; a gate formed above the active region proximate the upper surface of the active region and at least partially between the source and drain regions; and a shielding structure formed proximate the upper surface of the active region, the shielding structure being spaced laterally from the gate and overlapping at least a portion of the gate, the shielding structure being electrically connected at one end to the source region; wherein the at least one RF MOS transistor is configured such that during conduction under a potential applied to the drain region, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes at least a portion of the drift region between the shielding structure and the buried well, and wherein the transistor is configured to induce a velocity saturation mode of operation in the depleted drift region when the potential applied to the drain region is larger than an applied gate bias to thereby sustain a linear mode of operation of an inversion channel formed under the gate for all operating conditions of the transistor.