发明名称 |
Capacitive coupled sense amplifier biased at maximum gain point |
摘要 |
A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node coupled to a second bitline through a second capacitor, a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor, a first transmission gate switch coupled between the first input node and the second input node, a second transmission gate switch coupled between a first common node of the first and second inverters and a second common node of the first and second inverters. The sense amplifier is maintained at a maximum gain point in a read cycle. |
申请公布号 |
US8848474(B2) |
申请公布日期 |
2014.09.30 |
申请号 |
US201313746653 |
申请日期 |
2013.01.22 |
申请人 |
LSI Corporation |
发明人 |
Singh Sahilpreet |
分类号 |
G11C7/00;G11C7/06 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
1. A sense amplifier coupled between a complementary pair of first and second bitlines that are coupled to respective first and second global bitlines in a static random access memory (SRAM) cell, the sense amplifier comprising:
a first inverter including a first input node and a first output node, the first input node coupled to the first bitline through a first capacitor, the first output node coupled to the second bitline through a second capacitor; a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor; a first transmission gate switch coupled between the first input node and the second input node; and a second transmission gate switch coupled between a first common node of the first and second inverters and a second common node of the first and second inverters, wherein the sense amplifier is maintained at a maximum gain point in a read cycle of the SRAM cell. |
地址 |
San Jose CA US |