Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

摘要

In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

主权项

1. A memory circuit comprising:
a clock gater circuit configured to gate a clock signal in a first voltage domain with an enable signal in the first voltage domain to generate a first gated clock signal in the first voltage domain; a level shifter circuit configured to level shift and clock gate the clock signal with the enable signal to generate a second gated clock signal in a second voltage domain; and a wordline driver circuit in the second voltage domain and coupled to receive the first gated clock signal and the second gated clock signal, wherein the wordline driver circuit includes one or more discharging transistors that are coupled to the first gated clock signal and one or more charging transistors that are coupled to the second gated clock signal.