发明名称 Two-pass linear complexity task scheduler
摘要 A method for two-pass scheduling of a plurality of tasks generally including steps (A) to (C). Step (A) may assign each of the tasks to a corresponding one or more of a plurality of processors in a first pass through the tasks. The first pass may be non-iterative. Step (B) may reassign the tasks among the processors to shorten a respective load on one or more of the processors in a second pass through the tasks. The second pass may be non-iterative and may begin after the first pass has completed. Step (C) may generate a schedule in response to the assigning and the reassigning. The schedule generally maps the tasks to the processors.
申请公布号 US8850437(B2) 申请公布日期 2014.09.30
申请号 US201113290299 申请日期 2011.11.07
申请人 Avago Technologies General IP (Singapore) Pte. Ltd. 发明人 Shutkin Yurii S.;Aliseychik Pavel A.;Gasanov Elyar E.;Neznanov Ilya V.;Sokolov Andrey P.;Panteleev Pavel A.
分类号 G06F9/46;G06F9/50 主分类号 G06F9/46
代理机构 Christopher P. Maiorana, PC 代理人 Christopher P. Maiorana, PC
主权项 1. A method for two-pass scheduling of a plurality of tasks, comprising the steps of: (A) assigning each of said tasks to a corresponding one or more of a plurality of processors in a first pass through said tasks using a circuit, wherein (i) said first pass is non-iterative and (ii) at least one of said tasks is assigned to run on two or more of said processors in parallel; (B) reassigning said tasks among said processors to shorten a respective load on one or more of said processors in a second pass through said tasks, wherein said second pass (i) is non-iterative and (ii) begins after said first pass has completed; and (C) generating a schedule in response to said assigning and said reassigning, wherein said schedule maps said tasks to said processors, wherein said reassigning of said tasks in said second pass changes at least one of said tasks from being mapped to a single one of said processors to being mapped to at least two of said processors.
地址 Singapore SG