| 主权项 |
1. An integrated circuit design method, comprising:
determining a region in which power supply noise shall be analyzed, an initial area of the region and a number of initial decoupling capacitors to be used; determining current model parameters of the region; determining model parameters of a power supply network model corresponding to the initial area of the region; inputting into a simulator a net list of the region, the initial area of the region, the number of initial decoupling capacitors to be used by the region, current model parameters of the region, and model parameters of the power supply network model of the region, to obtain a simulation result; judging, based on the simulation result, whether or not the region satisfies noise requirements of a chip power supply, under the initial area of the region and the number of initial decoupling capacitors to be used by the region; and determining that the initial area is a minimum area that satisfies the noise requirements of the chip power supply in a case where the region uses the number of initial decoupling capacitors if the region satisfies noise requirements of the chip power supply, and further comprising: (i) in a case where region does not satisfy the noise requirements of the chip power supply, using the number of the initial decoupling capacitors to be used by the region as an initial value of the number of the current decoupling capacitors, increasing the number of the current decoupling capacitors by a prescribed value; judging if the number of the current decoupling capacitors reaches a threshold, wherein in a case where the number of the current decoupling capacitors does not reach the threshold, inputting into the simulator the current region, the area of the current region, the number of the current decoupling capacitors, the current model parameters, and the model parameters of the power supply network model to obtain a simulation result; judging if the region satisfies the noise requirements of the chip power supply under the area of the current region and the number of the current decoupling capacitors; determining that the current area is the minimum area that satisfies the noise requirements of the chip power supply in a case where the region uses the number of current decoupling capacitors when judging that the noise requirements of the chip power supply cannot be satisfied; returning to the step of increasing the number of the current decoupling capacitors by a prescribed value, when judging that the noise requirements of the chip power supply cannot be satisfied, and (ii) in a case where the number of the current decoupling capacitors reaches the threshold, using the initial area of the region as the initial value of the area of the current region and increasing the area of the current region by a prescribed value; re-determining the model parameters of the power supply network model corresponding to the area of the current region; recovering the number of the current decoupling capacitors to be its initial number; returning to the step of inputting into the simulator the current region, the area of the current region, the number of the current decoupling capacitors, the current model parameters, and the model parameters of the power supply network model to obtain a simulation result, and judging if the region satisfies the noise requirements of the chip power supply under the area of the current region and the number of the current decoupling capacitors; determining that the current area is the minimum area that satisfies the noise requirements of the chip power supply in a case where the region uses the number of current decoupling capacitors when judging that the noise requirements of the chip power supply are satisfied; and returning to the step of increasing the number of the current decoupling capacitors by a prescribed value, when judging that the noise requirements of the chip power supply cannot be satisfied. |
