Quantum-limited highly linear CMOS detector for computer tomography

摘要

The invention provides a CMOS CT detector design with high linearity, quantum-limited noise, good scalability, high fill factor with a single CMOS chip utilizing synchronous partial quantization. The CMOS CT detector includes a pixel array, digital column buses, analog column buses, column processing circuits, a shift register, a control signal generation circuit, and a reference generation circuit, and implements a synchronous partial quantization scheme with reset, integration and analog readout phases. Each pixel of the pixel array further includes a photodiode; an integration capacitor; an OPAMP; a reset switch; a comparator; a 1-bit dynamic random-access-memory (DRAM) cell; a circuit block for enabling subtraction of a substantially fixed amount of charge from the integrated photocharge if the integrated photovoltage increases beyond the reference voltage; an integration node; an analog buffer; and a switch coupled between the output of the DRAM cell and the digital column bus. The inclusion of a level-shifter and a current front-end improves the linearity of the detector.

主权项

1. A CMOS (complementary metal-oxide-semiconductor) CT (computed tomography) detector for implementing synchronous partial quantization, comprising:
a pixel array including a plurality of pixels arranged into at least one column; at least one digital column bus corresponding to the at least one column; at least one analog column bus corresponding to the at least one column; at least one column processing circuit corresponding to the at least one column for processing digital and analog outputs received from the at least one digital column bus and the at least one analog column bus; a shift register for multiplexing outputs of at least two column processing circuits; a control signal generation circuit for generating controls signals for at least one pixel of the plurality of pixels, the shift register, and the at least one column processing circuit; and a reference generation circuit for generating at least one voltage reference for at least one of: the at least one column processing circuit and the plurality of pixels; wherein the at least one pixel of the plurality of pixels includes:
a photodiode for generating a photocurrent;an integration capacitor, configured to increase an integrated photovoltage by being discharged by the photocurrent;an operational amplifier for establishing feedback to force the photocurrent to be integrated on the integration capacitor;a reset switch for resetting the integration capacitor during a reset phase;a comparator for comparing the integrated photovoltage with a reference voltage;a memory cell for recording the output of the comparator synchronously with a system clock;a circuit block for transferring a substantially fixed amount of charge from a sampling capacitor to the integration capacitor in response to a determination that the integrated photovoltage exceeds the reference voltage;an integration node connected to the input of the operation amplifier and to the integration capacitor;an analog buffer for receiving the integrated photovoltage at the end of an integration phase; anda switch coupled between the output of the memory cell and the digital column bus for driving the digital column bus during the integration phase.