Multiple write during simultaneous memory access of a multi-port memory device

摘要

A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.

主权项

1. A semiconductor memory, comprising:
a first set of bit line pairs, wherein a respective bit line pair of the first set of bit line pairs is connected to one or more respective first ports of one or more respective multi-port memory cells; a second set of bit line pairs, wherein a respective bit line pair of the second set of bit line pairs is connected to respective second ports of one or more respective one of the multi-port memory cells; and at least one pair of switch components, wherein each switch component in the pair of switch components is configured to connect a wire from the first set of bit line pairs to a wire from the second set of bit line pairs, wherein the wire from the first set of bit line pairs and the wire from the second set of bit line pairs are both connected to a same one or more multi-port memory cells of the multi-port memory cells.