发明名称 Low power receiver for implementing a high voltage interface implemented with low voltage devices
摘要 An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
申请公布号 US8847657(B2) 申请公布日期 2014.09.30
申请号 US201213530426 申请日期 2012.06.22
申请人 Avago Technologies General IP (Singapore) Pte. Ltd. 发明人 Kumar Pankaj;Parameswaran Pramod;Deshpande Vani;Kothandaraman Makeshwar
分类号 H03L5/00 主分类号 H03L5/00
代理机构 Christopher P. Maiorana, PC 代理人 Christopher P. Maiorana, PC
主权项 1. An apparatus comprising: a first stage configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad, wherein (A) said input signal is received at a source of a native device type transistor and (B) said first voltage is limited to a bias voltage received at a gate of said native transistor; and a second stage configured to generate a core voltage in response to said first voltage, wherein (i) said second stage comprises (a) a diode connected device configured to adjust a trip point of an output inverter to avoid the need to provide skewing, and (b) a current source configured to adjust a voltage threshold of said diode connected device, (ii) said second voltage received from said pad operates at a voltage compliant with one or more published interface specifications and (iii) said diode connected device has a gate and a source connected to said intermediate signal and a drain configured to generate said core voltage.
地址 Singapore SG