Dither control circuit and devices having the same

摘要

A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.

主权项

1. An integrated circuit device, comprising:
a pseudo random number generator configured to generate a pseudo random number sequence in response to a clock signal; and a dither circuit configured to dither an input digital code in response to at least one output bit in the pseudo random number sequence and further configured to output a digital code as a sum of or a difference between the input digital code and the dithered input digital code.