发明名称 SYSTEMS, APPARATUSES, AND METHODS FOR ZEROING OF BITS IN DATA ELEMENT
摘要 PROBLEM TO BE SOLVED: To provide systems, methods and apparatuses for execution of an instruction that uses a control vector to zero out bits starting at a specific position in each data element of a source in a SIMD processing system.SOLUTION: The execution of a VPBZHI causes, on a per data element basis of a second source, a zeroing of bits higher (more significant) than a starting point in the data element. The starting point is defined by the contents of a data element in a first source. The resultant data elements are stored in a corresponding data element position of a destination.
申请公布号 JP2014182800(A) 申请公布日期 2014.09.29
申请号 JP20140032531 申请日期 2014.02.24
申请人 INTEL CORP 发明人 ELMOUSTAPHA OULD-AHMED-VALL;ROBERT VALENTINE
分类号 G06F9/305;G06F9/315;G06F9/38 主分类号 G06F9/305
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