发明名称 |
SYSTEMS, APPARATUSES, AND METHODS FOR DETERMINING TRAILING LEAST SIGNIFICANT MASKING BIT OF WRITEMASK REGISTER |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide common operation means which in general makes it possible to adjust mask bits within writemask registers that correspond to elements in a vector register referred to in a SIMD operation instruction.SOLUTION: The execution of a KZBTZ detects a trailing least significant zero bit position in a first input mask and sets an output mask to have values of the first input mask, but with all bit positions closer to the most significant bit position than the trailing least significant zero bit position in a first input mask set to zero. In some embodiments, a second input mask is used as a writemask such that bit positions of the first input mask are not considered in the trailing least significant zero bit position calculation depending upon a corresponding bit position in the second input mask.</p> |
申请公布号 |
JP2014182796(A) |
申请公布日期 |
2014.09.29 |
申请号 |
JP20140028431 |
申请日期 |
2014.02.18 |
申请人 |
INTEL CORP |
发明人 |
CHRISTOPHER J HUGHES;MARK J CHARNEY;JESUS CORBAL;MILIND B GIRKAR;ELMOUSTAPHA OULD-AHMED-VALL;TOLL BRET L;ROBERT VALENTINE |
分类号 |
G06F9/305;G06F9/34;G06F9/38 |
主分类号 |
G06F9/305 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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