发明名称 Electronic Biasing Circuit for Constant Transconductance
摘要 An electronic biasing circuit provides a DC bias voltage to a circuit to be biased. The biasing circuit has a first transistor and a second transistor. A gate of the first transistor is connected to a gate of the second transistor and supplies the DC bias voltage. A source of the first transistor is connected to a supply reference voltage. A source of the second transistor is connected to the supply reference voltage via a resistor element. The currents flowing through the first and second transistor are forced to be equal. A third transistor is connected in series with the first transistor and a fourth transistor is connected in series with the second transistor. Currents flowing through the third and fourth transistors are forced to be equal.
申请公布号 US2014285265(A1) 申请公布日期 2014.09.25
申请号 US201313974320 申请日期 2013.08.23
申请人 Dialog Semiconductor B.V. 发明人 Papamichail Michail
分类号 H03F3/16 主分类号 H03F3/16
代理机构 代理人
主权项 1. An electronic biasing circuit arranged to provide a DC bias voltage to a circuit to be biased by said DC bias voltage, the biasing circuit comprising a first transistor pair comprising a first transistor and a second transistor both being of a first MOSFET type, a gate of said first transistor being connected to a gate of said second transistor and arranged to supply said DC bias voltage, a source of said first transistor being connected to a supply reference voltage, a source of said second transistor being connected to said supply reference voltage via a resistor element, in use a first current flowing through said first transistor and a second current flowing through said second transistor, the electronic biasing circuit comprising circuit components arranged to cause said first current and said second current to be substantially equal, wherein the biasing circuit comprises a second transistor pair comprising a third transistor and a fourth transistor of said same first MOSFET type, which third transistor is, at one side, connected in series with said first transistor at a first common node, and a gate of said third transistor being connected to a gate of said fourth transistor, a source of said fourth transistor being connected to a drain of said second transistor at a second common node, in use a third current flowing through said third transistor and a fourth current flowing through said fourth transistor, said circuit components also being arranged to cause said third current and said fourth current to be substantially equal.
地址 's-Hertogenbosch NL