发明名称 PROCESSOR SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To provide a variable capacity memory capable of reconfiguring the memory capacity.SOLUTION: The variable capacity memory having plural basic units comprises: a memory cell array whose basic unit has one cell transistor T0 and one resistance change element R0; a mode selector 1B that selectively switches between a first mode in which 1 bit reading/writing is made on 2(n is an integer) basic units in the plural basic units and a second mode in which 1 bit reading/writing is made on 2(m is an integer; n≠m) basic units in the plural basic units; and a control circuit that controls the switching between the first mode and the second mode.</p>
申请公布号 JP2014179150(A) 申请公布日期 2014.09.25
申请号 JP20130053661 申请日期 2013.03.15
申请人 TOSHIBA CORP 发明人 NOGUCHI HIROKI;FUJITA SHINOBU;ABE KEIKO
分类号 G11C11/15;G06F12/08 主分类号 G11C11/15
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