COHERENCE DE-COUPLING BUFFER

摘要

A coherence decoupling buffer. In accordance with a first embodiment, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality of cache memories. A coherence decoupling buffer may be free of value information of the plurality of cache memories. A coherence decoupling buffer may also be combined with a coherence memory.

主权项

1. An apparatus comprising:
a plurality of cache memories configured to store cache line tags and cache line data; a coherence memory configured to store the cache line tags that are stored in the plurality of cache memories; and a coherence decoupling buffer coupled to the plurality of cache memories and the coherence memory and configured to store an evicted cache line tag of a cache line evicted from the plurality of cache memories.