| 主权项 |
1. A processor comprising:
a plurality of processing units, each including a first cache memory, and each configured to perform an arithmetic operation and to output an access request; a second cache memory configured to cache data that are arithmetically processed respectively by any of the plurality of processing units, the second cache memory being shared between or among the plurality of processing units; an acquiring unit configured to acquire from an access request to data cached in the second cache memory, lock target information including first storage location information of the data in a first cache memory included in one of the plurality of processing units, the access request being issued from the one of the plurality of processing units; a retaining unit configured to retain the lock target information until response processing to the access request is completed; and a control unit configured to control an access request issued to the second cache memory from any one of the plurality of processing units, the access request being related to a replace request to replace target data retained in a first cache memory of the one of the plurality of processing units, based on second storage location information of the target data in the first cache memory, the second storage location information included in the access request being related to the replace request, and first storage location information included in the lock target information retained in the retaining unit. |
